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CY28RS480
Clock Generator for ATI RS480 Chipset
Features
* Supports AMD CPU * 200-MHz differential CPU clock pairs * 100-MHz differential SRC clocks * 48-MHz USB clock * 33-MHz PCI clock * 66-MHz HyperTransport clock * I2C support with readback capabilities * Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction * 3.3V power supply * 56-pin SSOP and TSSOP packages CPU x2 SRC x8 HTT66 x1 PCI x1 REF x3 USB_48 x1
Block Diagram
XIN XOUT CPU_STP# CLKREQ[0:1]#
Pin Configuration
VDD_REF REF[0:2] VDD_CPU CPUT[0:1], CPUC[0:1], VDD_SRC SRCT[0:5],SRCC[0:5] VDD_SRCS SRCST[0:1],SRCSC[0:1] VDD_PCI PCI VDD_HTT HTT66
XTAL OSC PLL1
PLL Ref Freq
Divider Network
IREF
PD
VDD_48 MHz
PLL2
USB_48
SDATA SCLK
I2C Logic
XIN XOUT VDD_48 USB_48 VSS_48 NC SCLK SDATA NC CLKREQ#0 CLKREQ#1 SRCT5 SRCC5 VDD_SRC VSS_SRC SRCT4 SRCC4 SRCT3 SRCC3 VSS_SRC VDD_SRC SRCT2 SRCC2 SRCT1 SRCC1 VSS_SRC SRCST1 SRCSC1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
VDD_REF VSS_REF REF0 REF1 REF2 VDD_PCI PCI0 VSS_PCI VDD_HTT HTT66 VSS_HTT CPUT0 CPUC0 VDD_CPU VSS_CPU CPUT1 CPUC1 VDDA VSSA IREF VSS_SRC1 VDD_SRC1 SRCT0 SRCC0 VDD_SRCS VSS_SRCS SRCST0 SRCSC0
56 SSOP/TSSOP
CY28RS480
Cypress Semiconductor Corporation Document #: 38-07638 Rev. *C
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised February 21, 2005
CY28RS480
Pin Description
Pin No. 41,40,45,44 50 37 52, 53, 54 7 8 27, 28, 30, 29 12, 13, 16, 17, 18, 19, 22, 23, 24, 25, 34, 33 10,11 Name CPUT/C PCI0 IREF REF[2:0] SCLK SDATA SRCST/C[1:0] SRCT/C[5:0] Type O I 33-MHz clock output. A precision resistor attached to this pin is connected to the internal current reference. SMBus-compatible SCLOCK.This pin has an internal pull-up, but is tri-stated in power-down. Description O, DIF Differential CPU clock outputs. AMD K8 buffer (200 Mhz).
O, SE 14.318-MHz REF clock output. Intel Type-5 buffer. I,PU
I/O,PU SMBus-compatible SDATA.This pin has an internal pull-up, but is tri-stated in power-down. O, DIF Differentials Selectable serial reference clock. Intel Type-X buffer. Includes overclock support through SMBUS O, DIF 100-MHz differential serial reference clock. Intel Type-X buffer.
CLKREQ#[0:1]
I, SE, Output Enable control for SRCT/C. Output enable control required by Minicard PD specification. This pin has an internal pull-down. 0 = Selected SRC outputs are enabled, 1 = Selected SRC outputs are disabled O, SE 48-MHz clock output. Intel Type-3A buffer. O, SE 66-MHz clock output. Intel Type-5 buffer. PWR PWR PWR PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND GND GND GND I O 3.3V power supply for USB outputs 3.3V power supply for CPU outputs 3.3V power supply for PCI outputs 3.3V power supply for REF outputs 3.3V power supply for Hyper Transport outputs 3.3V power supply for SRC outputs 3.3V power supply for SRC outputs 3.3V power supply for SRCS outputs 3.3V Analog Power for PLLs Ground for USB outputs Ground for CPU outputs Ground for PCI outputs Ground for REF outputs Ground for SRC outputs Ground for SRC outputs Ground for SRCS outputs Ground for HyperTransport outputs Analog Ground 14.318-MHz Crystal Input 14.318-MHz Crystal Output No Connects
4 47 3 43 51 56 48 14, 21 35 32 39 5 42 49 55 15, 20, 26 36 31 46 38 1 2 6, 9
USB_48 HTT66 VDD_48 VDD_CPU VDD_PCI VDD_REF VDD_HTT VDD_SRC VDD_SRC1 VDD_SRCS VDDA VSS_48 VSS_CPU VSS_PCI VSS_REF VSS_SRC VSS_SRC1 VSS_SRCS VSS_HTT VSSA XIN XOUT NC
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CY28RS480
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h).
Table 1. Command Code Definition Bit 7 (6:5) (4:0) Chip select address, set to `00' to access device Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000' Description 0 = Block read or block write operation, 1 = Byte read or byte write operation
Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 37 45:38 46 .... .... .... .... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte /Slave Acknowledges Data Byte N - 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 46:39 47 55:48 56 .... .... .... Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 Start Slave address - 7 bits Write Acknowledge from slave Description Bit 1 8:2 9 10 Start Slave address - 7 bits Write Acknowledge from slave Byte Read Protocol Description Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte Count from slave - 8 bits Acknowledge Data byte 1 from slave - 8 bits Acknowledge Data byte 2 from slave - 8 bits Acknowledge Data bytes from slave / Acknowledge Data Byte N from slave - 8 bits NOT Acknowledge Block Read Protocol Description
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CY28RS480
Table 3. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit 18:11 19 27:20 28 29 Description Command Code - 8 bits Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop Bit 18:11 19 20 27:21 28 29 37:30 38 39 Byte Read Protocol Description Command Code - 8 bits Acknowledge from slave Repeated start Slave address - 7 bits Read Acknowledge from slave Data from slave - 8 bits NOT Acknowledge Stop
Control Registers
Byte 0:Control Register 0 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name SRC[T/C]5 SRC[T/C]4 SRC[T/C]3 SRC[T/C]2 SRC[T/C]1 SRC [T/C]0 SRCS[T/C]1 SRCS[T/C]0 SRC[T/C]5 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRCS[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRCS[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Description
Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name REF2 REF1 REF0 PCI0 USB_48 RESERVED CPU[T/C]1 CPU[T/C]0 REF2 Output Enable 0 = Disable, 1 = Enable REF1 Output Enable 0 = Disable, 1 = Enable REF0 Output Enable 0 = Disable, 1 = Enable PCI0 Output Enable 0 = Disable, 1 = Enable USB_48MHz Output Enable 0 = Disable, 1 = Enable RESERVED CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Description
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CY28RS480
Byte 2: Control Register 2 Bit 7 @Pup 1 Name CPUT/C SRCT/C USB_48 PCI Reserved Reserved CPU SRC Reserved Reserved Spread Spectrum Selection `0' = -0.35% `1' = -0.50% 48-MHz Output Drive Strength 0 = 2x, 1 = 1x 33-MHz Output Drive Strength 0 = 2x, 1 = 1x Reserved Reserved CPU/SRC Spread Spectrum Enable 0 = Spread off, 1 = Spread on Reserved Reserved Description
6 5 4 3 2 1 0
1 1 0 1 0 1 1
Byte 3: Control Register 3 Bit 7 @Pup 1 Name CLKREQ# Description CLKREQ# drive mode 0 = SRC clocks driven when stopped, 1 = SRC clocks tri-state when stopped CPU pd drive mode 0 = CPU clocks driven when power-down, 1 = CPU clocks tri-state SRC pd drive mode 0 = SRC clocks driven when power-down, 1 = SRC clocks tri-state Reserved Reserved Reserved Reserved HTT66 Output Drive Strength0 = High drive, 1 = Low drive.
6 5 4 3 2 1 0
0 1 0 1 1 1 1
CPU SRC Reserved Reserved Reserved Reserved HTT66
Byte 4: Control Register 4 Bit 7 @Pup 0 Name SRC[T/C]5 Description SRC[T/C]5 CLKREQ0 control 1 = SRC[T/C]5 stoppable by CLKREQ#0 pin 0 = SRC[T/C]5 free running SRC[T/C]4 CLKREQ#0 control 1 = SRC[T/C]4 stoppable by CLKREQ#0 pin 0 = SRC[T/C]4 free running SRC[T/C]3 CLKREQ#0 control 1 = SRC[T/C]3 stoppable by CLKREQ#0 pin 0 = SRC[T/C]3 free running SRC[T/C]2 CLKREQ#0 control 1 = SRC[T/C]2 stoppable by CLKREQ#0 pin 0 = SRC[T/C]2 free running SRC[T/C]1 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running SRC[T/C]0 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running HTT66 Output enable 0 = Disabled, 1 = Enabled
6
0
SRC[T/C]4
5
0
SRC[T/C]3
4
0
SRC[T/C]2
3
0
SRC[T/C]1
2
0
SRC[T/C]0
1
1
HTT66
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CY28RS480
Byte 4: Control Register 4 (continued) Bit 0 @Pup 1 Name Reserved Reserved Description
Byte 5: Control Register 5 Bit 7 @Pup 0 Name SRC[T/C]5 Description SRC[T/C]5 CLKREQ#1 control 1 = SRC[T/C]5 stoppable by CLKREQ#1 pin 0 = SRC[T/C]5 free running SRC[T/C]4 CLKREQ#1 control 1 = SRC[T/C]4 stoppable by CLKREQ#1 pin 0 = SRC[T/C]4 free running SRC[T/C]3 CLKREQ#1 control 1 = SRC[T/C]3 stoppable by CLKREQ#1 pin 0 = SRC[T/C]3 free running SRC[T/C]2 CLKREQ#1 control 1 = SRC[T/C]2 stoppable by CLKREQ#1 pin 0 = SRC[T/C]2 free running SRC[T/C]1 CLKREQ#1 control 1 = SRC[T/C]1 stoppable by CLKREQ#1 pin 0 = SRC[T/C]1 free running SRC[T/C]0 CLKREQ#1 control 1 = SRC[T/C]1 stoppable by CLKREQ#1 pin 0 = SRC[T/C]1 free running Reserved Reserved
6
0
SRC[T/C]4
5
0
SRC[T/C]3
4
0
SRC[T/C]2
3
0
SRC[T/C]1
2
0
SRC[T/C]0
1 0
0 0
Reserved Reserved
Byte 6: Control Register 6 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 1 HW HW HW HW Name TEST_SEL TEST_MODE REF Reserved Reserved Reserved Reserved Reserved Description REF/N or Three-state Select 1 = REF/N Clock, 0 = Three-state Test Clock Mode Entry Control 1 = REF/N or Tri-state mode, 0 = Normal operation REF Output drive strength 0 = Low drive, 1 = High drive Reserved Reserved Reserved Reserved Reserved
Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 1 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description
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CY28RS480
Table 4. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 35 ppm Stability (max.) 30 ppm Aging (max.) 5 ppm
Crystal Recommendations
The CY28RS480 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28RS480 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading.
series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides.
Clock Chip
Ci1
Ci2 Pin 3 to 6p
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It's a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true.
Cs1 X1 X2
Cs2 Trace 2.8pF
XTAL Ce1 Ce2
Trim 33pF
Figure 2. Crystal Loading Example As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2.
Figure 1. Crystal Capacitive Clarification
Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) CLe
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in
=
1 ( Ce1 + Cs1 + Ci1 +
1
1 Ce2 + Cs2 + Ci2
)
CL ....................................................Crystal load capacitance CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.) CL ....................................................Crystal load capacitance CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.)
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CY28RS480
CLK_REQ[0:1]# Description The CLKREQ#[1:0] signals are active low input used for clean stopping and starting selected SRC outputs. The outputs controlled by CLKREQ#[1:0] are determined by the settings in register bytes 4 and 5. The CLKREQ# signal is a debounced signal in that its state must remain unchanged during two consecutive rising edges of DIFC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.) CLK_REQ[0:1]# Deassertion [Low to High Transition] The impact of deasserting the CLKREQ#[1:0] pins is all DIF outputs that are set in the control registers to stoppable via assertion of CLKREQ#[1:0] are to be stopped after their next transition. When the control register CLKREQ# drive mode bit is programmed to `0', the final state of all stopped SRC signals is SRCT clock = High and SRCC = Low. There is to be no change to the output drive current values, SRCT will be driven high with a current value equal 6 x Iref,. When the control register CLKREQ# drive mode bit is programmed to `1', the final state of all stopped DIF signals is low, both SRCT clock and SRCC clock outputs will not be driven. CLK_REQ[0:1]# Assertion [High to Low Transition] All differential outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the Assertion to active outputs is between 2-6 SRC clock periods (2 clocks are shown) with all SRC outputs resuming simultaneously. If the CLKREQ# drive mode bit is programmed to `1' three-state), the all stopped SRC outputs must be driven high within 10 ns of CLKREQ#[1:0] Assertion to a voltage greater than 200 mV.
CLKREQ#X
SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable)
Figure 3. CLK_REQ#[0:1] Assertion/Deassertion Waveform
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CY28RS480
Absolute Maximum Conditions
Parameter VDD VDDA VIN TS TA TJ ESDHBM OJC OJA UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Relative to VSS Non-functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - 2000 - - V-0 1 Max. 4.6 4.6 VDD+0.5 +150 70 150 - 20 60 Unit V V VDC C C C V C/W C/W
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter Description 3.3V 5% Condition Min. 3.135 Max. 3.465 Unit V VDD_REF, 3.3V Operating Voltage VDD_CPU, VDD_PCI, VDD_SRC, VDD_SRC1, VDD_SRCS VDD_48 VILSMBUS VIHSMBUS VIL VIH IIL VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD IPDD IPDT Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage High-Impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power Down Supply Current Power Down Supply Current At max load and frequency PD asserted, Outputs driven PD asserted, Outputs Hi-Z Except pull-ups or pull-downs 0SDATA, SCLK SDATA, SCLK VDD
- 2.2 VSS-0.3 2.0 -5 - 2.4 -10 3 3 - 0.7*VDD 0 - - -
1.0 0.8 VDD+0.3 5 0.4 - 10 5 5 7 VDD 0.3*VDD 450 75 12
V V V V mA V V A pF pF nH V V mA mA mA
AC Electrical Specifications
Parameter Crystal TDC TPERIOD Description XIN Duty Cycle Condition The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Min. 47.5 Max. 52.5 Unit %
XIN Period
69.841
71.0
ns
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CY28RS480
AC Electrical Specifications (continued)
Parameter TR / TF TCCJ LACC Description XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long-term Accuracy Condition Measured between 0.3VDD and 0.7VDD As an average over 1-s duration Over 150 ms Measured @ test load using VOCM 400 mV, 0.85 to 1.65 Measured at load single ended Measured at crossing point VOX Measured at load single ended Measured at load single ended Measured at load single ended Measured at VOX Measured at VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) Min. - - - 2 0.4 - -150 1.05 -200 45 0 45 9.997001 9.997001 10.12800 9.872001 - - - - 175 - - - Math averages Figure 5 Math averages Figure 5 660 -150 250 - -0.3 See Figure 5. Measure SE - - Measured at 1.5V Measured at 20% and 60% Measured at 1.5V Measurement at 1.5V 45 0.9 - - Max. 10.0 500 300 7 2.3 250 150 1.45 200 55 200 55 10.00300 10.05327 9.872001 10.17827 250 250 125 300 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 66.67 55 6.5 450 500 Unit ns ps ppm V/ns V ps mV V mV % ps % ns ns ns ns ps ps ps ppm ps % ps ps mv mv mV V V V MHz % V/ns ps ps
CPU Outputs TR/TF Output Slew Rate VDIFF TSKEW _ VDIFF VCM _ VCM TDC TJCYC SRC TDC TPERIOD TPERIODSS TPERIODAbs Differential Voltage Any CPU to CPU Clock Skew Change in VDIFF_DC Magnitude Common Mode Voltage Change in VCM Duty Cycle Cycle to Cycle Jitter SRCT and SRCC Duty Cycle 100-MHz SRCT and SRCC Period 100-MHz SRCT and SRCC Absolute Period
100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX
TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Period, SSC TSKEW TSKEW TCCJ LACC TR / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB Any SRCT/C to SRCT/C Clock Skew Any SRCS clock to Any SRCS clock Skew SRCT/C Cycle to Cycle Jitter SRCT/C Long Term Accuracy SRCT and SRCC Rise and Fall Times Rise/Fall Matching Rise TimeVariation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage
HTT66 HyperTransport Output F66 Operating Frequency TDC TR/TF TCCJ TSKEW Duty Cycle Slew Rate Cycle to Cycle jitter HTT66 clock to PCI clock Skew
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CY28RS480
AC Electrical Specifications (continued)
Parameter PCI TDC TPERIOD TPERIODSS TPERIODAbs THIGH TLOW TR / TF TCCJ USB TDC TPERIOD TPERIODAbs THIGH TLOW TR / TF TCCJ TLTJ REF TDC TPERIOD TPERIODAbs TR / TF TCCJ PCI Duty Cycle Spread Disabled PCI Period Spread Enabled PCI Period, SSC Spread Disabled PCI Period PCI high time PCI low time PCI rise and fall times PCI Cycle to Cycle Jitter Duty Cycle Period Absolute Period USB high time USB low time Rise and Fall Times Cycle to Cycle Jitter Long Term Jitter REF Duty Cycle REF Period REF Absolute Period REF Rise and Fall Times REF Cycle to Cycle Jitter Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V@1 us Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V 45 29.99100 29.9910 29.49100 29.49100 12.0 12.0 1.0 - 45 20.83125 20.48125 8.094 7.694 1.0 - - 45 69.8203 68.82033 1.0 - - 10.0 0 55 30.00900 30.15980 30.50900 30.65980 - - 4.0 500 55 20.83542 21.18542 10.036 9.836 2.0 350 TBD 55 69.8622 70.86224 4.0 1000 1.8 - - % ns ns ns ns ns ns V/ns ps % ns ns ns ns V/ns ps ps % ns ns V/ns ps ms ns ns Description Condition Min. Max. Unit
TPERIODSSAbs Spread Enabled PCI Period, SSC
ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up TSS TSH Stopclock Set-up Time Stopclock Hold Time
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CY28RS480
Test and Measurement Set-up
For PCI Single-ended Signals and Reference The following diagram shows the test load configurations for the single-ended PCI, USB, and REF output signals.
12 60
PCI/ USB
Measurement Point
5pF
12
60
Measurement Point
5pF
22
60
Measurement Point
5pF
22
60
REF
22 60
Measurement Point
5pF
Measurement Point
5pF
Figure 4. Single-ended Load Configuration For Differential CPU and SRC Output Signals The following diagram shows the test load configuration for the differential SRC outputs.
33 100 4 9 .9 33 100 4 9 .9
SRCT
M e a s u re m e n t P o in t
2pF
SRCC IR E F
475
M e a s u re m e n t P o in t
2pF
Figure 5. 0.7V Load Configuration
3 .3 V s ig n a l s
-
T DC
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V 0V
TR
TF
Figure 6. Single-ended Output Signals (for AC Parameters Measurement)
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CY28RS480
Vbias=1.25V 125 ohms 169 ohms 15 ohms 3900pF 5pF 5pF 125 ohms
15 ohms
3900pF
Figure 7. CPU Output Load Configuration
Ordering Information
Part Number Lead-free Package Type Product Flow
CY28RS480OXC CY28RS480OXCT CY28RS480ZXC CY28RS480ZXCT
56-pin SSOP 56-pin SSOP - Tape and Reel 56-pin TSSOP 56-pin TSSOP - Tape and Reel
Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C
Package Drawing and Dimensions
56-Lead Shrunk Small Outline Package O56
.020
28 1
0.395 0.420 0.292 0.299
DIMENSIONS IN INCHES MIN.
MAX.
29
56
0.720 0.730 SEATING PLANE 0.088 0.092 0.095 0.110
GAUGE PLANE
.010
0.005 0.010
0.025 BSC
0.110 0.008 0.0135 0.008 0.016 0-8
0.024 0.040
51-85062-*C
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CY28RS480
Package Drawing and Dimensions (continued)
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
0.249[0.009]
28 1
DIMENSIONS IN MM[INCHES] MIN. MAX.
7.950[0.313] 8.255[0.325] 5.994[0.236] 6.198[0.244]
REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG.
29
56
13.894[0.547] 14.097[0.555]
1.100[0.043] MAX.
GAUGE PLANE 0.25[0.010]
0.20[0.008]
0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.051[0.002] 0.152[0.006] SEATING PLANE 0-8
0.508[0.020] 0.762[0.030]
0.170[0.006] 0.279[0.011]
0.100[0.003] 0.200[0.008]
51-85060-*C
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ATI is a registered trademark of ATI Technologies Inc. HyperTransport is a trademark of the HyperTransport Technology Consortium. Intel and Pentium are registered trademarks of Intel Corporation. AMD is a registered trademark of Advanced Micro Devices, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07638 Rev. *C
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY28RS480
Document History Page
Document Title: CY28RS480 Clock Generator for ATI RS480 Chipset Document Number: 38-07638 REV. ECN NO. Issue Date Orig. of Change Description of Change
** *A *B
204582 215828 267850
See ECN See ECN See ECN
RGL RGL RGL
New data sheet Minor change: posted to external web site Changed pins 10 and 11 from internal Pull up to Pull down Changed polarity of CLKREQ# Added register byte 3 bits [1:3] for CPU Stop control Changed the Slew rate to max of 6.5V/ns Changed the IDD max load from 400 to 450 mA Changed the IPD Outputs Driven from 70 to 75 mA Changed the CPU Duty Cycle from 45 to 53 to 45 to 55% Changed the HTT66 Cycle to cycle jitter from 300 to 450 ps Fixed the Single-ended loading diagram Fixed the ordering information table to match the parts in the DevMaster
*C
325360
See ECN
RGL
Document #: 38-07638 Rev. *C
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